Data processor module for a modular data processing system for operation with a time-shared memory in the simultaneous execution of multi-tasks and multi-programs



May 9, 1967 L E. MOTT ETAL DATA PROCESSOR MODULE FDR A MGDULAR DATA PROCESSING SYSTEM FOR OPERATION WITH A TIME-SHARED MEMORY IN THE SIMULTANEOUS EXECUTION OF MULTI-TASKS AND MULTI-PROGRAMS Filed Nov. 50, 1962 SUBCOMMANDS CONTROLS 07 Sheets-Sheet 1 MULTIPLY-DIVIDE COUNTERID) {DI I THIN FILM ADDRESS EATING SYLLIIBLE REGIS) I2 BITS FUNCTION REG. (F) I2 BITS MASK REGIPIIQ) 23 BITS I TEF SUITE AFIITHMETIC UNIT TEAJEBJEC 3 2 TDB TMAJMB B REGISTER 48 BITS V303 INTERRUPT ADDER 052 SIGNALS A REGISTER 4s BITS CREGISTER IZBITS \5030 1 I 1 5055 5054 F IGIB INVENTORS. LUCILE E. MOTT RONALD B. LOUNSBURY BY gFfiTEJE'EXSEEQw FIGIIB FIGI IIIIE ST II ZL DIfi'IQ a? mu ATTORNEY y 9, 1967 L. E. MOTT ETAL 3,319,226

DATA PROCESSOR MODULE FOR A MODULAR DATA PROCESSING SYSTEM FOR OPERATION WITH A TIME-SHARED MEMORY IN THE SIMULTANEOUS EXECUTION OF MULTI-TASKS AND MULTI-PROGRAMS Filed Nov. 30, 1962 107 Sheets-Sheet 5 K REG.

E3, 5 (W1 0: Q Q 981 00 I 031 Q O co a E E 2: #0 8 93 m (\J O5 Q s 2% 314g vsw I Q N N3 r0 g E" 0% N) I I?) w I N v (\J 2 1 vsvj :3 Q g LL. :1? O I 1 I N) an m cn Pg VQVJ E m 5% m k A m 55 IOVH 5 5% 1 V N 8V1 $4 w W1 (\J o m a: VWJ a HD VEIHHS g 2 .i VINl W G)" V31 IVJ s31 V91 r*rt s x [L 5; z Z|9|HHS w w E ,5 3 f D 5 2 5 E INVENTORS. 32 E2 Lu LUCILE E, MOTT W E a RONALD a. LOUNSBURY Q: a w 0: BY BLAIR c. THOMPSON he 5 a J J 5. PETER BEAUREGARD 2 4... y JAMES L. MumAusH,un. a O (In: o: o 2 AUGUST ASAR INAS a: 0 II E: a: E: c: o: 8 Q: Li.) G 2 2: Lu :3 z (44 Q E ATTORNEY L. E. MOTT ETAL 3,319,226

MODULAR DATA PROCESSING SYS May 9, 1967 A R n O 6 F h S S M E 5 T ..b N e A 8 5.3 MS

SHARED MEMURY IN THE SIMULT MAGNETIC DRUMS (TWO PER CABINET) MAGNETIC 0 0 FILE SUPERVlSDRY iNTERSYSTEM 1 DATA LINKS MAGNETIC TA PE TRANSPORT PAPER TAPE PERFORATOR HIGH-SPEED AUTOMATIC INPUT/OUTPUT EXCHANGE L C [L N m m m m E E W H m M M C B Y 0m PW m m m m m WNMMA M II Y 0 R E DH N BOGU I. M A P S E mm Y WUNP M Dn U URR 0 N OOAU T F M H MS M s M m A E U w v v UU mAmU u D CNA MG T P J UOL .AU mv LRBS A /.L u m GK m mm U W m S m l l I I uTPuT EXCHANGE W U DI| WHHHIE Pu .7 1' T M W A IF IL 8 5 m0 K R R C E PT! 0 MN LL mm W m mm W M O H H 5 S l A A EL D R R M w R 1! AU rr m l 9 F m R m H E. MOTT ETAL 3,319,226

A MODULAR DATA PROCESSING SYSTEM FOR May 9, 1967 L. DATA PROCESSOR MODULE FOR OPERATION WITH A TIME-SHARED MEMORY IN THE SIMULTANEOUS EXECUTION OF MULTI-TASKS AND MULTI-PHOGRAMS 1962 107 Sheets-Sheet b STORE FETCH DIRECTION DIRECTION FIG.6B

Filed Nov. 30,

FIGOA FIRST OPERAND IN STACK (A IS STACK) AMNDEXED SECOND OPERAND ADDRESS IN CORE MEMORY ,//,IIIDEXED STORE IOGAIIOM INCORIEMEMORY I 4 M I I r I IIIOIOI I I I OT DI 7L 7 I25456 T8 9|O|II2 v W HAW CORE MEMORY INDEXING INFO. CROE MEMORY INSTRUCTION A2 A5 RELATIVE ADDRESS FOR STORE RELATIVE ADDRESS CODE FOR SECOND OPERANO ADDRESS OF STORE LOCATION BAD TAGS FIRST SYLLABLE SECOND SYLLABLE THIRD SYLLABLE FOURTH SYLLABLE 0 (M) I (M) SYMBOLIC DESCR|PTION1A|+A2 -A5 PROGRAM SYLLABLE PROGRAM SYLLABLE PROGRAM SYLLABLE PROGRAM SYLLABLE PROGRAM WORD Igsn I2 BITS I2 BITS I2RIIs CHARACTERCHARACIE GIARAGIER CHARACTER OHARACIERCHARACTER GIIARAOIEROIIARAOTER AIPHANUMERIC 0 l 2 5 4 5 6 T UAIAWORD 6BITS ORIIs BBITS GRIIs GBITS GBITS BBITS sans RIMARY DATA i BINARY FRACTION z; W RD I BIT 4TBITS g BINARY FLOATING- EI QIE EXPONENT MASNID'DSA (BINARY FRACTION) POIIII OAIA I H BUS MANTISSA WORD FBH' FBH' 35 BITS I= INVENTORS. Q=+ LUCILE E. MOTT RONALD BI LOUNBURY FI G. 5 BY EF IEEI EE9ADSEIEIIRQ JAMES L. MURTAUGH AUGUST A, SARDINA ATTORNEY y 9, 1967 L. E. MOTT ETAL 3,319,226

DAT/I PROCESSOR MODULE FOR A MODULAR DATA PROCESSING SYSTEM FOR OPERATION WITH A TIME-SHARED MEMORY IN THE SIMULTANEOUS EXECUTION OF MULTI-TASKS AND MULTI-PROGRAMS Filed Nov. 30, 1962 107 Sheets-Sheet BITS BITS l 2IT {ISIS 7A8 9AI|0 IAIZ I 2 3I4 T'TINIT a 9I|OII|II2 T. 2 3 "J- BASE ADDRESS INCREMENT 0 IIIMMAIIO TAc TAG TAT; I I

I I I I I INDEX REG. INDEX REG.

ADDRESS ADDRESS ADDRESS MACHINE CONDITION FLAGS I I I I I I I I I I I I I N OOUNTOFREPETITIONS CORE MEMORY I I I I I I I REIIIIIIEIOPEIIAIIIIAIIIIIIESI III INCREMENT INCREMENT INCREMENT "s" NATNANT SHIFTAMOUNT .T T CORE MEMORY AETATTNT BRANCH ADDRESS CHARACTER "T" NAN THINFILMREGADDRESS IIZIBJIYIYEATBALTQLQ T' T2 .WBII N III |25456?89IOH I2 I. "THIN 'T A BITS m WMABIEF E ,V ,ZI5 I.L5WQ L I JIQ J I I T sTTTTT FIELD FIELD BIIS AMOUNT LENGTH BEGIN I 2 5 I I I I I I I "v VARIANT "151 1 IINCREMENTAMOUNT I I I I I I I "v" NARTANT .T T. INDEX REG. LIMITREG. T T IIIIIIIIIIII ADDRESS ADDRESS T TI25456789I0HI2 I BITS w VARIANT F I98 I T T T T T T T T T M INVENTORST .T CORE MEMORY LUCILE E. 0 J RONALD B.LO NSBURY q T RETIIIIVEIDDREIST BY AususT'A.sARoT-A's TTTTUAEI I I T W ATTORNEY 3,319,226 YSTEM FOR May 9, 1967 L. E. MOTT ETAL MODULAR DATA PROCESSING S -SHARED MEMORY IN THE SIMULTANEOUS ULTI -TASKS AND MULTI-PROGRAMS A R E 0 FM E W A U N T I w swm SIE T A 0 RR E P 0 T A D 10? Sheets-Sheet 8 Filed Nov. 50, 1962 mOE mmdE

qmO E May 9, 1967 E. MOTT ETAL MODULAR DATA PROCESSING SYSTEM FOR SHARED MEMORY IN THE SIMULTANEOUS TASKS AND MULTI-PROGRAMS A T T. m E U Fm E T M L A U N w I e w m Sm T 0 A R E P A O T A D 107 Sheets-Sheet 9 Filed Nov. 30, 1962 mmOE May 9, 1967 DATA PROCESSOR MODULE FOR A MODULAR DATA PROCESSING S L. E. MOTT ETAL YSTEM FOR OPERATION WITH A TIME-SHARED MEMORY IN THE SIMULTANEOUS EXECUTION OF MULTI-TASKS AND MULTI-PROGRAMS Filed NOV. 30, 1962 107 Sheets-Sheet 12 PH1-T1 PHITI t See power 3 Flt/g IS the power failure f il flip-flop (IPF) set? routine Reset the D counter Fl 12 Reset the SY counter Reset the IS counter the MC P' Is the halt condttton Jump to Hose! the BRF f l1pf10p flipJmp (HTC) Sm? TU Resrt the IRJ l'llp-flop PHI T1 Is the real time See the PHI-T4 clock interrupt Wm lock t t. r t Is this instruction p p lri z a Ito-address -4-- Fig. 3 instructinn'? N0 Yeg Sec the H11 FA PHPT Is one of the mterrupt inter-rum reg. bits (I) set? routine Jump to HLT F 1Q PH?! TI instruction H See the N Y ts this a "repeated 11H) T4 mstructlon? instructiun. 1 N0 Fig 15 Comm PHI-T1! T? YES 5 h V n I ee t e No SE0 SHR Is a F LL requued {in Exezutc Yes No ti 71 PHl- J t t 1;; 1 Fig. 24 I m In hm 111R Xwut, Fetch the uperatut' from thv MIL PSI-t at the address indicated by the PS counter, and VH1 store this npzerutnr in the lnstrm'tl m F reg. ('umplvtlw].

Jump tn T1 mum V Pin-T4 Slt the Set the I H1 r5 normal halt Instruction mmhv condition complvted. intvrrupt F-F Jump to (1H!) (HTC) T! May 9, 1967 E. MOTT ETAL 3,319,226

DATA PROCESSOR MODULE FOR A MODULAR DATA PROCESSING SYSTEM FOR OPERATION WITH A TIME-SHARED MEMORY IN THE SIMULTANEOUS EXECUTION OF MULTI-TASKS AND MULTI-PROGRAMS 1962 Filed Nov.

107 Sheets-Sheet 13 V umauags W5 wuguwa f mou n85 FE -3 .3302 5.3. v5 .S U m2. Arm

H 3 E. SE 3 53m A1 Em 9533 nwion w mam nEdumEm 33803 2: 3

oh. 2 mean vB QEo wc nam SLE MP oInm QQOE MTHLIQ NHPLEm y 9, 1967 L. E. MOTT ETAL 3,319,225

DATA PROCESSOR MODULE FOR A MODULAR DATA PROCESSING SYSTEM FOR OPERATION WITH A TIMESHARED MEMORY IN THE SIMULTANEUUS EXECUTION OF MULTI-TASKS AND MULTI-PROGRAMS Filed Nov. 30, 1962 107 Sheets-Sheet 14 IHB-T 2 P HB-Tli, 4 Read the 12 least significant I m tth t ncz e en 9 51A! )1 c of the RTC roun RTC Count y ne PH3-T5 PUB-T5 Store the new HTC vount bark in thin film N0 Did incrementing produce carry? Yes PHB-TLZ PH3T3,4 F the most Sig Increment these most want bits or significant bits by one count 7 PUB-T5 PUB-T5 Store this syllable back in thin film No Did inrrementing produce carry Yes PUB-T4 V s the mask bit (Q5) for the Real Time lock set? Yes I-H3-'I4 1/ Set ihe Real Time Clock interrupt (I5) I! if {V R93! Time (10 k update completed Jump to PHI -Tl FIGI3 y 9, 1967 E. MOTT ETAL 3,319,226

DATA PROCESSOR MODULE FOR A MODULAR DATA PROCESSING SYSTEM FOR OPERATION WITH A TIME-SHARED MEMORY IN THE SIMULTANEOUS EXECUTION OF MULTI-TASKS AND MULTI-PROGRAMS Filed Nov. 30, 1962 107 Sheets-Sheet 15 lnlgggpt ljgutine Jumg (Automatic routinc upon receipt of an intcrrupt othvr' than power failure or rval time interrupt.)

IlH-Tl PH1T7,T8

SM lH-J. Stow Lhu rontcnts 01' Yhv Store the contents of the program first group 111 control flip-flops in I storage reg. (PSR) in thc intmrupt thv mlcrrupt dump reg. (IDR) program reg. (IPR) Set the Control Tins group includes: Mode flip-flop. (INT) PS1, PS2, PS3, RPF, FRP, PF PFZ, PUV, PUN, INN, SA}, 5A2, PH3-T1,T2

r P SF. T P and R X he Store the contents of the base oi thvsc control Eb are stored m I address reg. (BAR) 1n the bzts 1 through 15 of the mterrupt r mterrupt storage reglster. (15R) lump mg.

least s1gn1f1cant locatlon.

PH3-T3 T4 Y t Y. t J l H3 If) Store tho contPnts of the bane howl thc contents of the program TE'g. (BPH) in th nvxt program count reg (PCB) least sLgmficant locanon o1 ISR PHIFTH l PBS-T6, T7

lJiri an overlap occur imme- Yes Subtract one from the dlately preceding the interrupt? program count No PHB-T8 I I Store the program count in thc n'xust significant location of the ISR of tho interrupt bung sm'vicml into Store tho contents of the inte-rrupt thc M rwg. Add tlns numbPr to thv base address reg.(IAR) in the BAR intcrrnpt hast addrvss and store the and the BPR.

result in thc VCR.

PH3-T12 y 9, 1967 L. E. MOTT ETAL 3,319,226

DATA PROCESSOR MODULE FOR A MODULAR DATA PROCESSING SYSTEM FOR OPERATION WITH A TIME-SHARED MEMORY IN THE SIMULTANEOUS EXECUTIQN OF MULTI-TASKS AND MULTI-PROGRAMS Filed Nov. 50, 1962 107 Sheets-Sheet l6 PHI-Tl, 7, 8,9

PHl-Tl Read the repeat count. Set Repeat Flip- Flop (RPF) Decremem it by Hl-T9w Repeat Count 0? PHI-T10 Store decremented repeat count in the Repeat Count Register (RCR) PH1-TH,2,3

Fetch operator syllable J from Repeat Program Reg. (RPR), store in F Reg.

SUBSEQUENT PHASE DEPENDING ON INSTRUCTION Perform operation indicated by operator:

1) First time instruction is repeated, contents of Base Address Register (BAR) are added to memory relative address syllable, contents of Base Program Register (BPR) are added to branch relative address syllable, and result is stored in Repeat Program Reg. (HPR) 2) Indirect addressing may be used on first repetition a l 3) After first repetition, indexing accomplished automatically by adding contents of appropriate portion of Repeat Increment Register (RIR) to 16-bit direct address in corresponding portion of Repeat Program Register (KPH).

4) U branch occurs before the repeat count reduces to zero, program will branch and both RPF and FR? flipflops will be reset.

PHI-TS PHI-T9 p t. C 1 t d Reset Repeat and First v e e Re eat Fli -Flo s RPF,,

Jump to PHI-T1 g, p p

y 9, 1967 L. E. MOTT ETAL 3,319,226

DATA PROCESSOR MODULE FOR A MODULAR DATA PROCESSING SYSTEM FOR OPERATION WITH A TIME-SHARED MEMORY IN THE SIMULTANEQUS EXECUTION OF MULTI -TASKS AND MULTI -PROGRAMS Filed Nov. 30, 1962 107 Sheets-Sheet 1'? T1 through T9 Memory Compute A ddress 9 Stack or Memory, Routine (Fig 27) T10 T10, 15 through T15 TM19 through TM28 Operand Transfer from Operand Transfer from Stack to Arithmetic Unit Routine (Fig. 30)

Main Memory to Arith. Unit Routine (Fig. 29)

Is Instruction YE JTl JTI JPH4 @JPHB T10, T15 T1 through T9 TM3 through TMB Compute Memory re "1\' Register Address Routine in Mam Memory (Fig. 27) Routine (Fig. 31)

T1 Memory is Instrui-tion JT] MW 01' "SI-JR? JPHI through T13 'ii'unsfi-r l'lxtirrnal Store "A" Hcgistor Hoquvst Lmvs to in Stock Routine "A" itfigister (Fig. 32)

PHE PHZ T10, T15 T1 through '19 TMIQ through TMZH Compute Memory Branch Program Word Address of Branch Transfer Main Memory JTl Program Routine to Program Storage Reg- JPHI (Fig. 28) ister Routine (Fig. 33)

FIG. l8

May 9, 1967 1.. MOTT ETAL 3,319,226 DATA PROCESSOR MODULE FOR A MODULAR DATA PROCESSING SYSTEM FOR OPERATION WITH A TIME-SHARED MEMORY IN THE SIMULTANEOUS EXECUTION OF MULTI-TASKS AND MULTI-PROGRAMS Filed Nov. 50, 1962 107 Sheets-Sheet l8 T10, T15 T1 through 9 TM19 through TMZB C m no Add, Operand Transfer from 2 i (H T Main Memory to Arith Unit Routine (Fig. 29)

Memory n JPlili Stack or Floating Instruction? JTl St k R T10 through T15 JPH5 operand Transfer from Stack to Arithmetic I Unit Routine (Fig. 30)

T10, T15 Tl through T9 TM3 through TMB Compute Memory Store "A" Register Address Instruction in Main Memory Routine (Fig. 27) Routine (Fig. 31) 7 J r1 T13 or JPHi Memory T15 Yes Stack OI Instruction "CBF" "LCM" Memory? "STE" "TBS"? Stack A T10 throu gh T13 N0 JPHS Store IIAII Register T1301 T15 1'85 in Stack Routine Instruction (Fig. 32)

May 9, 1967 E. MOTT ETAL 3,319,226 DATA PROCESSOR MODULE FOR A MODULAR DATA PROCESSING SYSTEM FOR OPERATION WITH A TIME-SHARED MEMORY IN THE SIMULTANEOUS EXECUTION 0F MULTI-TASKS AND lIUL'lI-PROGRAMS Filed Nov. 30, 1962 10? Sheets-Sheet 19 TM 19 through TM 28 Compute Memory Address Branch Program Word Transfer oi Branch Program word Main Memory to Program Storage Routine (Fig. 28) Register Routine (Fig. 33)

L, m FIG.2I

110,113 n T! through T9 TM3 through TMB I ll Compute A dr i yt l l lzin Mfi ii' R utine (8- 27) Routine E- JT] -W T10 through T13 (Fig. 32)

FIG.22

T10, T13 TM19 through TMZB Tl through T9 Compute Memory Address of Branch Program Word D' Routine (Fig. 28)

Branch Program Word Transfer Main Memory to Program Storage Register Routine (Fig. 33)

FIG.23

y 9, 1967 L. E. MOTT ETAL 3,319,226

DATA PROCESSOR MODULE FOR A MODULAR DATA PROCESSING SYSTEM FOR OPERATION WITH A TIME-SHARED MEMORY IN THE SIMULTANEOUS lQEXECUTION OF MULTI'TASKS AND MULTIPROGRAMS 107 Sheets-Sheet 20 Filed Nov. 30.

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31. A COMPUTER ADAPTED TO PROVIDE UP TO THREE-ADDRESS PROGRAMMING CAPABILITY AND VARIABLE LENGTH INSTRUCTIONS, SAID COMPUTER COMPRISING: AN ARITHMETIC UNIT, A SUBCOMMAND MATRIX AND CONTROLS PORTION, A FAST-ACCESS, THIN-FILM MEMORY PORTION, AND A MEMORY EXCHANGE PORTION, SAID SUBCOMMAND MATRIX AND CONTROLS PORTION INCLUDING A PHASE DISTRIBUTOR TO PROVIDE UP TO THREE-ADDRESS CAPABILITY, SAID PHASE DISTRIBUTOR PROVIDING MEANS TO PROVIDE A PLURALITY OF OPERATING PHASES, MEANS RESPONSIVE TO JUMP SUBCOMMANDS TO MOVE FROM PHASE TO PHASE, SAID JUMP SUBCOMMANDS MEANS BEING SUBCOMMAND MARTIX MEANS RESPONSIVE TO AN INSTRUCTION BEING EXECUTED, MEANS RESPONSIVE TO A JUMP SUBCOMMAND TO EFFECT A RESET-PHASE SIGNAL TO PROVIDE AN INPUT TO SAID PHASE DISTRIBUTOR COMPRISING, A PLURALITY OF PHASE FLIP-FLOPS INCLUDING A PHASE JUST EXECUTED FLIP-FLOP AND AN ENTRY PHASE FLIP-FLOP FOR THE PHASE NEXT TO BE EXECUTED. 